Integrated circuits, such as microprocessors and memories, routinely transmit data to one another. However, an integrated circuit receiving data may not be able to process the data immediately upon receipt because the integrated circuit is in the midst of other operations. For example, a memory may not be able to access data from some memory cells whose addresses are transmitted from a microprocessor because the memory is performing other internal operations. Therefore, buffers are necessary at the inputs of many integrated circuits, such as memories. Data, such as a memory address, is stored in the buffer until the integrated circuit is ready to process the data
Because the integrated circuit may require the received data immediately, the buffer should be fast. Conventional buffers include circuitry, such as multiplexors and permanent feedback loops, to latch the address. FIG. 1 illustrates a prior art buffer 100, including successively coupled input, gain, and output stages 102, 104, 114. The prior art buffer includes a multiplexor 110 and an inverter latch 112 in its output stage 114. An address signal, A.sub.IN, is sampled and inverted by the input stage 102 when a relatively low voltage is applied at EN* (or address enable signal complement). When ADDR TRAP (or address trap signal) is biased with a relatively low voltage, the multiplexor 110 couples the sampled address signal into the output stage 114 where the sampled address signal is latched at the inverter latch 112, and further inverted to provide A.sub.out (or latched address signal).
At least five gate delays are encountered in this buffer, greatly diminishing the speed of the buffer. Buffer speed is also reduced by the permanent feedback loop formed by the inverter latch 112 which requires relatively more time to change its state.
There is a need to increase buffer speed. Thus, there is a further need to reduce the circuitry in the path that the sampled address signal must travel in the buffer while maintaining the ability to reliably buffer addresses.